1. Field of the Invention
The invention relates generally to a semiconductor element and a manufacturing method thereof. More particularly, the invention relates to a semiconductor element such as a BiCDMOS (bipolar-CMOS-DMOS) element having a bipolar transistor, a complementary metal oxide semiconductor (CMOS) transistor and a double diffused metal oxide semiconductor (DMOS) transistor formed on a single substrate.
2. Description of the Related Technology
As is well known, BiCDMOS semiconductor elements provide the low power consumption, low noise margin and high integration density of CMOS technology, the fast switching and input/output speed of bipolar technology, and the high voltage characteristics of DMOS technology. As a result, BiCDMOS technology enables power elements, logic elements, etc. to be integrated within a single chip, thereby providing high current driving capability while minimizing the size and power consumption of the chip and increasing the resistance of the chip to high voltages (e.g., electrostatic discharge, supply overvoltage, etc.).
Generally speaking, the techniques typically used to manufacture a BiCDMOS semiconductor element are a combination of the techniques used to manufacture bipolar, CMOS and DMOS elements. However, the manufacture of BiCDMOS semiconductor elements is extremely complicated and requires a large number of mask layers. In particular, manufacturing a BiCDMOS semiconductor element requires the gate electrodes of the CMOS element and the DMOS element to be formed in different processes to achieve stability of the CMOS and DMOS elements. More specifically, after the gate electrode of the DMOS element is formed, ion implantation or channel ion injection for adjusting a threshold voltage of the CMOS element is performed, which is followed by the formation of the gate electrode of the CMOS element. To perform this process, part of the polysilicon layer is left remaining to act as a side wall spacer on a side wall of the gate electrode of the DMOS element while etching a polysilicon layer that forms the gate electrode of the CMOS element.
In semiconductor elements of submicron sizes that require a shallow junction or a diffused region, the side wall spacer present on the side wall of the gate electrode of the DMOS element results in an open (e.g., an open circuit or high impedance region) between the conduction channels that are induced by the source regions and the gate electrode of the DMOS element. This open between the channels results in an undesirable increase in a threshold voltage of the semiconductor element. In turn, such an increase in the threshold voltage prevents the semiconductor element from operating at a gate voltage permitted by the particular semiconductor element.